This invention relates to programmable logic, and in particular to a programmable logic device that can be reconfigured in whole or in part without the use of an external memory device.
A programmable logic device (PLD) is a programmable integrated circuit that allows the user of the circuit, using software control, to customize the logic functions the circuit will perform. The logic functions previously performed by small, medium and large scale integration integrated circuits can instead be performed by programmable logic devices. When a typical programmable logic device is supplied by an integrated circuit manufacturer, it is not yet capable of performing any specific function. The user, in conjunction with software supplied by the programmable logic device manufacturer, can program the PLD to perform the specific function or functions required by the user's application. The PLD then can function in a larger system designed by the user, just as though dedicated logic chips were employed.
A typical PLD consists of an array of logic cells that can be individually programmed and arbitrarily interconnected to each other to provide internal input and output signals, thus permitting the performance of highly complex combinational and sequential logic functions. The program is implemented in the PLD by setting the states of programmable elements such as memory cells. These memory cells may be implemented with volatile memories, such as SRAMs, which lose their programmed states upon termination of power to the system, or with non-volatile memories, such as EPROMs or EEPROMs, which retain their contents upon termination of power. If the programmable elements used are volatile memories, the memory cells must be reconfigured upon system power-up in order to restore the PLD to the desired programmed state. The reconfiguration step is achieved by saving the configured states in an external non-volatile memory device that will save the PLD configuration even after power-down. Then, when power is restored to the system, the configured states of the memory cells are serially loaded from the non-volatile external memory device to the PLD.
This method of PLD reconfiguration forces the system designer to include additional control logic dedicated to serial loading of configuration data from the external memory device every time the system is powered up. Furthermore, each time the configuration of the PLD is altered, a new external non-volatile memory device must be inserted into the system, making system design changes cumbersome and increasing the expense of the system as more and more design changes are implemented.
Accordingly, it would be preferable to reconfigure the PLD upon power-up without resorting to the use of an external non-volatile memory device.